SH7050 Datasheet, PDF (53/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
2.3.3 Instruction Format
Table 2.9 lists the instruction formats for the source operand and the destination operand. The
meaning of the operand depends on the instruction code. The symbols are used as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx xxxx
0
xxxx
Source
Operand
—
Destination
Operand
—
Example
NOP
n format
15
xxxx nnnn
0
xxxx xxxx
m format
15
xxxx mmmm xxxx
0
xxxx
—
Control register
or system
register
Control register
or system
register
mmmm: Direct
register
mmmm: Indirect
post-increment
register
mmmm: Direct
register
mmmm: PC
relative using
Rm
nnnn: Direct
register
nnnn: Direct
register
MOVT Rn
STS MACH,Rn
nnnn: Indirect
pre-decrement
register
Control register or
system register
Control register or
system register
STC.L
LDC
LDC.L
SR,@-Rn
Rm,SR
@Rm+,SR
—
JMP @Rm
—
BRAF Rm
Rev. 5.00 Jan 06, 2006 page 33 of 818
REJ09B0273-0500