SH7050 Datasheet, PDF (394/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
13.2.3 Transmit Shift Register (TSR)
The transmit shift register (TSR) transmits serial data. The SCI loads transmit data from the
transmit data register (TDR) into the TSR, then transmits the data serially from the TxD pin, LSB
(bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data
from the TDR into the TSR and starts transmitting again. If the TDRE bit of the SSR is 1,
however, the SCI does not load the TDR contents into the TSR.
The CPU cannot read or write the TSR directly.
Bit: 7
6
5
4
3
2
1
0
R/W: —
—
—
—
—
—
—
—
13.2.4 Transmit Data Register (TDR)
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When
the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the
TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset,
in hardware standby mode and software standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Jan 06, 2006 page 374 of 818
REJ09B0273-0500