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SH7050 Datasheet, PDF (476/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/
Section 14 A/D Converter
14.5 Interrupt Sources and DMA Transfer Requests
The A/D converter can generate an A/D conversion end interrupt request (ADI0 or ADI1) upon
completion of A/D conversions. The ADI interrupt can be enabled by setting the ADIE bit in the
A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0.
The DMAC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the
CPU.
When the DMAC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically
cleared when data is transferred by the DMAC.
See section 9.4.3, Example of DMA Transfer between A/D Converter and Internal Memory, for an
example of this operation.
14.6 Usage Notes
The following points should be noted when using the A/D converter.
1. Analog input voltage range
The voltage applied to analog input pins during A/D conversion should be in the range AVSS ≤
ANn ≤ AVref.
2. Relation between AVCC, AVSS and VCC, VSS
When using the A/D converter, set AVCC = VCC ±10%, and AVSS = VSS. When the A/D
converter is not used, set AVSS = VSS , and do not leave the AVCC pin open.
3. AVref input range
Set AVref = 4.5 V to AVCC when the A/D converter is used, and AVref ≤ AVCC when not used..
If conditions 1, 2, and 3 above are not met, the reliability of the device may be adversely
affected.
4. Notes on board design
In board design, digital circuitry and analog circuitry should be as mutually isolated as
possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or
are in close proximity should be avoided as far as possible. Failure to do so may result in
incorrect operation of the analog circuitry due to inductance, adversely affecting A/D
conversion values.
Also, digital circuitry must be isolated from the analog input signals (ANn), analog reference
voltage (AVref), and analog power supply (AVCC) by the analog ground (AVSS). The AVSS
should be connected at one point to a stable digital ground (VSS) on the board.
Rev. 5.00 Jan 06, 2006 page 456 of 818
REJ09B0273-0500