SH7050 Datasheet, PDF (135/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

8.2 Description of Registers
Section 8 Bus State Controller (BSC)
8.2.1 Bus Control Register 1 (BCR1)
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
A3SZ A2SZ A1SZ A0SZ
Initial value: 0
0
0
0
1
1
1
1
R/W: R
R
R
R
R/W R/W R/W R/W
BCR1 is a 16-bit read/write register that specifies the bus size of the CS spaces.
Write bits 15–0 of BCR1 during the initialization stage after a power-on reset, and do not change
the values thereafter. In on-chip ROM effective mode, do not access any of the CS spaces until
after completion of register initialization. In on-chip ROM ineffective mode, do not access any CS
space other than CS0 until after completion of register initialization.
BCR1 is initialized to H'000F by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode.
Bits 15–4—Reserved: These bits always read as 0. The write value should always be 0.
Bit 3—CS3 Space Size Specification (A3SZ): Specifies the CS3 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Bit 3: A3SZ
0
1
Description
Byte (8 bit) size
Word (16 bit) size (initial value)
Bit 2—CS2 Space Size Specification (A2SZ): Specifies the CS2 space bus size. A 0 setting
specifies byte (8-bit) size, and a 1 setting specifies word (16-bit) size.
Rev. 5.00 Jan 06, 2006 page 115 of 818
REJ09B0273-0500