SH7050 Datasheet, PDF (250/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 2:
IOxx2
0
Bit 1:
IOxx1
0
Bit 0:
IOxx0
0
1
1
0
1
1
0
0
1
1
0
1
Description
GR is an output
compare register
GR is input capture
register
0 output regardless of compare-match
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge
Input capture in GR on falling edge
Input capture in GR on both rising and
falling edges
Timer I/O Control Registers 3A, 3B, 4A, 4B, 5A (TIOR3A, TO0R3B, TIOR4A, TIOR4B,
TIOR5A)
Timer I/O control registers 3A, 3B, 4A, 4B, and 5A (TIOR3A, TO0R3B, TIOR4A, TIOR4B,
TIOR5A) are 8-bit registers. There are five TIOR registers, two each for channels 3 and 4, and one
for channel 5.
TIOR3A
Bit:
Initial value:
R/W:
7
CCI3B
0
R/W
6
IO3B2
0
R/W
5
IO3B1
0
R/W
4
IO3B0
0
R/W
3
CCI3A
0
R/W
2
IO3A2
0
R/W
1
IO3A1
0
R/W
0
IO3A0
0
R/W
TIOR3B
Bit:
Initial value:
R/W:
7
CCI3D
0
R/W
6
IO3D2
0
R/W
5
IO3D1
0
R/W
4
IO3D0
0
R/W
3
CCI3C
0
R/W
2
IO3C2
0
R/W
1
IO3C1
0
R/W
0
IO3C0
0
R/W
TIOR3A and TIOR3B are 8-bit readable/writable registers. When bit 0 of TMDR is 0, they
specify whether general registers GR3A to GR3D are used as input capture or compare-match
registers, and also perform edge detection and output value setting. Also, when bit 0 of TMDR is
0, they select enabling or disabling of free-running counter (TCNT3) clearing.
Rev. 5.00 Jan 06, 2006 page 230 of 818
REJ09B0273-0500