SH7050 Datasheet, PDF (160/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Chan-
nel Name
Abbrevi-
Initial
ation
R/W Value
Address
Register Access
Size
Size
3
DMA source address SAR3
R/W Undefined H'FFFF86F0 32 bit 16, 32^*2
register 3
DMA destination
address register 3
DAR3
R/W Undefined H'FFFF86F4 32 bit 16, 32^*2
DMA transfer count DMATCR3 R/W Undefined H'FFFF86F8 32 bit 32^*3
register 3
DMA channel control CHCR3
register 3
R/W^*1 H'00000000 H'FFFF86FC 32 bit
16, 32^*2
Shared DMA operation
register
DMAOR R/W^*1 H'0000
H'FFFF86B0 16 bit 8, 16^*4
Notes: Registers are accessed in three cycles when using word access and six cycles when using
longword access.
Do not attempt to access an empty address.
1. Write 0 after reading 1 in bit 1 of CHCR0–CHCR3 and in bits 1 and 2 of the DMAOR to
clear flags. No other writes are allowed.
2. For 16-bit access of SAR0–SAR3, DAR0–DAR3, and CHCR0–CHCR3, the 16-bit value
on the side not accessed is held.
3. DMATCR has a 24-bit configuration: bits 0–23. Writing to the upper 8 bits (bits 24–31)
is invalid, and these bits always read 0.
4. Do not make 32-bit access for DMAOR.
9.2 Register Descriptions
9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the
source address of a DMA transfer. These registers have a count function, and during a DMA
transfer, they indicate the next source address. In single-address mode, SAR values are ignored
when a device with DACK has been specified as the transfer source.
Specify a 16-bit boundary when performing 16-bit data transfers, and a 32-bit boundary when
performing 32-bit data transfers. Operation cannot be guaranteed if any other addresses are set.
The initial value after power-on resets and in software standby mode is undefined.
Rev. 5.00 Jan 06, 2006 page 140 of 818
REJ09B0273-0500