SH7050 Datasheet, PDF (334/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Internal data bus
H
CPU
Bus
interface
1st write operation
H
Internal buffer
register
Module data
bus
TCNT0H
TCNT0L
Internal data bus
L
CPU
Bus
interface
2nd write operation
Module
L
Internal buffer ^{H data bus}
register
Module data bus
Figure 10.38 Write to TCNT0
TCNT0H
TCNT0L
10.5.2 Registers Requiring 16-Bit Access
Free-running counters 1 to 9 (TCNT1 to TCNT9), the general registers (GR), down-counters
(DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty
registers (DTR), and timer start register (TSTR) are 16-bit registers. These registers are connected
to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of
OSBR) a word at a time.
Figure 10.39 shows the operation when performing a word read or write access to TCNT1.
CPU
Internal data bus
Bus
interface
Module data bus
Figure 10.39 TCNT1 Read/Write Operation
TCNT1
Rev. 5.00 Jan 06, 2006 page 314 of 818
REJ09B0273-0500