SH7050 Datasheet, PDF (662/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 21 Power-Down State
Table 21.1 Power-Down State Conditions
State
Mode
Entering
Procedure Clock CPU
On-Chip
CPU
Peripheral
I/O
Registers Modules RAM Ports
Canceling
Procedure
Hardware Low-level Halted Halted Halted
standby input at
HSTBY pin
Software Execute
Halt Halt Held
standby SLEEP
instruction
with SBY bit
set to 1 in
SBYCR
Undefined
Halt^*1
Held^*2 Initialized High-level
input at
HSTBY pin,
executing
power-on
reset
Held
Held or
high
impe-
dance^*3
• NMI
interrupt
• Power-on
reset
Sleep
Execute
Run Halt Held
Run
SLEEP
instruction
with SBY bit
set to 0 in
SBYCR
Held Held
• Interrupt
• DMAC
address
error
• Power-on
reset
Notes: 1. SBYCR: standby control register. SBY: standby bit
2. Some bits within on-chip peripheral module registers are initialized by the standby
mode; some are not. Refer to table 21.3, Register States in the Standby Mode, in
section 21.4.1, Transition to Standby Mode. Also refer to the register descriptions for
each peripheral module.
3. The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of
the SBYCR. Refer to section 21.2, Standby Control Register (SBYCR). For pin status
other than for the I/O port, refer to Appendix B, Pin States.
Rev. 5.00 Jan 06, 2006 page 642 of 818
REJ09B0273-0500