SH7050 Datasheet, PDF (580/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
Start
*1
Set SWE bit in FLMCR1
Wait 10 µs
n=1
Set EBR1
*3
WDT Enable
Set ESU-bit of FLMCR1
Wait 200 µs
Set E-bit of FLMCR1
Wait 5ms
Erase start
Clear E-bit of FLMCR1
Wait 10 µs
Clear ESU-bit of FLMCR1
Wait 10 µs
WDT Disable
Set EV-bit of FLMCR1
Wait 20 µs
Erase stop
Set top block address to verify address
n←n+1
Dummy write H'FF to verify address
Wait 2 µs
Address
increment
NG
Read verify data
Verify data = all "1"?
OK
Last block address?
OK
Clear EV-bit of FLMCR1
*2
NG
Clear EV-bit of FLMCR1
Wait 5 µs
Wait 5 µs
NG ^*4
All
objective blocks
erased?
OK
Clear SWE-bit in FLMCR1
NG
n ≥ 61?
OK
Clear SWE-bit of FLMCR1
Erase complete
Erase error
Notes: 1. Preprogramming (setting erase block data to all “0”) is not necessary.
2. Verify data is read in 32-bit (longword) units.
3. Set only one bit in EBR1. More than one bit cannot be set.
4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Figure 18.8 Erase/Erase-Verify Flowchart
Rev. 5.00 Jan 06, 2006 page 560 of 818
REJ09B0273-0500