SH7050 Datasheet, PDF (737/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Interval Interrupt Request Register
(ITVRR)
H'FFFF8282 (Channel 0) 8
ATU
Bit: 7
6
5
4
Bit name: ITVAD3 ITVAD2 ITVAD1 ITVAD0
Initial value: 0
0
0
0
R/W: R/W R/W R/W R/W
3
ITVE3
0
R/W
2
ITVE2
0
R/W
1
ITVE1
0
R/W
0
ITVE0
0
R/W
Bit
Bit Name
Value Description
7
A/D converter interval
0
A/D converter activation by ATU is disabled
activation bit 3 (ITVAD3)
(Initial value)
1
A/D converter activation by ATU is enabled
6
A/D converter interval
0
A/D converter activation by ATU is disabled
activation bit 2 (ITVAD2)
(Initial value)
1
A/D converter activation by ATU is enabled
5
A/D converter interval
0
A/D converter activation by ATU is disabled
activation bit 1 (ITVAD1)
(Initial value)
1
A/D converter activation by ATU is enabled
4
A/D converter interval
0
A/D converter activation by ATU is disabled
activation bit 0 (ITVAD0)
(Initial value)
1
A/D converter activation by ATU is enabled
3
Interval interrupt bit 3
0
Interval interrupt generation is disabled
(ITVE3)
(Initial value)
1
Interval interrupt generation is enabled
2
Interval interrupt bit 2
0
Interval interrupt generation is disabled
(ITVE2)
(Initial value)
1
Interval interrupt generation is enabled
1
Interval interrupt bit 1
0
Interval interrupt generation is disabled
(ITVE1)
(Initial value)
1
Interval interrupt generation is enabled
0
Interval interrupt bit 0
0
Interval interrupt generation is disabled
(ITVE0)
(Initial value)
1
Interval interrupt generation is enabled
Rev. 5.00 Jan 06, 2006 page 717 of 818
REJ09B0273-0500