SH7050 Datasheet, PDF (139/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Bit 3: SW3
0
1
Bit 2: SW2
0
1
Bit 1: SW1
0
1
Bit 0: SW0
0
1
Section 8 Bus State Controller (BSC)
Description
No CS3 space CS assert extension
CS3 space CS assert extension (initial value)
Description
No CS2 space CS assert extension
CS2 space CS assert extension (initial value)
Description
No CS1 space CS assert extension
CS1 space CS assert extension (initial value)
Description
No CS0 space CS assert extension
CS0 space CS assert extension (initial value)
8.2.3 Wait Control Register 1 (WCR1)
Bit:
Initial value:
R/W:
15
W33
1
R/W
14
W32
1
R/W
13
W31
1
R/W
12
W30
1
R/W
11
W23
1
R/W
10
W22
1
R/W
9
W21
1
R/W
8
W20
1
R/W
Bit:
Initial value:
R/W:
7
W13
1
R/W
6
W12
1
R/W
5
W11
1
R/W
4
W10
1
R/W
3
W03
1
R/W
2
W02
1
R/W
1
W01
1
R/W
0
W00
1
R/W
WCR1 is a 16-bit read/write register that specifies the number of wait cycles (0–15) for each CS
space.
WCR1 is initialized by a power-on reset and in hardware standby mode to H'FFFF. It is not
initialized by software standby mode.
Bits 15–12—CS3 Space Wait Specification (W33, W32, W31, W30): Specifies the number of
waits for CS3 space access.
Rev. 5.00 Jan 06, 2006 page 119 of 818
REJ09B0273-0500