SH7050 Datasheet, PDF (739/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Timer Interrupt Enable Register A
(TIERA)
Bit: 7
6
Bit name: —
—
Initial value: 0
0
R/W: R
R
Appendix A On-Chip Supporting Module Registers
H'FFFF8284 (Channel 0) 8
ATU
5
4
3
2
1
0
— OVE0 ICE0D ICE0C ICE0B ICE0A
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W
Bit
Bit Name
Value Description
4
Overflow interrupt enable 0
OVI0 interrupt requested by OVF0 flag is disabled
(OVE0)
(Initial value)
1
OVI0 interrupt requested by OVF0 flag is enabled
3
Input capture interrupt 0
ICI0D interrupt requested by ICF0D flag is disabled
enable (ICE0D)
(Initial value)
1
ICI0D interrupt requested by ICF0D flag is enabled
2
Input capture interrupt 0
ICI0C interrupt requested by ICF0C flag is disabled
enable (ICE0C)
(Initial value)
1
ICI0C interrupt requested by ICF0C flag is enabled
1
Input capture interrupt 0
ICI0B interrupt requested by ICF0B flag is disabled
enable (ICE0B)
(Initial value)
1
ICI0B interrupt requested by ICF0B flag is enabled
0
Input capture interrupt 0
ICI0A interrupt requested by ICF0A flag is disabled
enable (ICE0A)
(Initial value)
1
ICI0A interrupt requested by ICF0A flag is enabled
Rev. 5.00 Jan 06, 2006 page 719 of 818
REJ09B0273-0500