SH7050 Datasheet, PDF (398/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RxI)
requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set to
1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables receive-
error interrupt (ERI) requests.
Bit 6: RIE
0
1
Description
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are disabled (initial value). RxI and ERI interrupt requests can
be cleared by reading the RDRF flag or error flag (FER, PER, or ORER)
after it has been set to 1, then clearing the flag to 0, or by clearing RIE
to 0.
Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)
requests are enabled.
Bit 5—Transmit Enable (TE): Enables or disables the SCI serial transmitter.
Bit 5: TE
0
1
Description
Transmitter disabled (initial value). The transmit data register empty bit
(TDRE) in the serial status register (SSR) is locked at 1.
Transmitter enabled. Serial transmission starts when the transmit data
register empty (TDRE) bit in the serial status register (SSR) is cleared
to 0 after writing of transmit data into the TDR. Select the transmit
format in the SMR before setting TE to 1.
Bit 4—Receive Enable (RE): Enables or disables the SCI serial receiver.
Bit 4: RE
0
1
Description
Receiver disabled (initial value). Clearing RE to 0 does not affect the
receive flags (RDRF, FER, PER, ORER). These flags retain their
previous values.
Receiver enabled. Serial reception starts when a start bit is detected in
the asynchronous mode, or synchronous clock input is detected in the
clock synchronous mode. Select the receive format in the SMR before
setting RE to 1.
Rev. 5.00 Jan 06, 2006 page 378 of 818
REJ09B0273-0500