SH7050 Datasheet, PDF (112/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
6.5 Interrupt Response Time
Table 6.5 indicates the interrupt response time, which is the time from the occurrence of an
interrupt request until the interrupt exception processing starts and fetching of the first instruction
of the interrupt service routine begins. Figure 6.5 shows the pipeline when an IRQ interrupt is
accepted.
Table 6.5 Interrupt Response Time
Item
DMAC active judgment
Number of States
NMI, Peripheral
Module
IRQ
0 or 1
1
Compare identified inter- 2
3
rupt priority with SR mask
level
Wait for completion of
X (≥ 0)
sequence currently being
executed by CPU
Time from start of interrupt 5 + m1 + m2 + m3
exception processing until
fetch of first instruction of
exception service routine
starts
Notes
1 state required for interrupt
signals for which DMAC
activation is possible
The longest sequence is for
interrupt or address-error
exception processing (X = 4
+ m1 + m2 + m3 + m4). If an
interrupt-masking instruction
follows, however, the time
may be even longer.
Performs the PC and SR
saves and vector address
fetch.
Interrupt
response
time
Total: 7 + m1 + m2 + m3
Minimum: 10
Maximum: 12 + 2 (m1 + m2 +
m3) + m4
8 + m1 + m2 + m3
11
12 + 2 (m1 + m2 +
m3) + m4
0.50 to 0.55 µs at 20 MHz
0.95 µs at 20 MHz^*
Note:
m1–m4 are the number of states needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
* When m1 = m2 = m3 = m4 = 1
Rev. 5.00 Jan 06, 2006 page 92 of 818
REJ09B0273-0500