SH7050 Datasheet, PDF (661/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 21 Power-Down State
Section 21 Power-Down State
21.1 Overview
In the power-down state, the CPU functions are halted. This enables a great reduction in power
consumption.
21.1.1 Power-Down States
The power-down state is effected by the following three modes:
1. Hardware standby mode
A transition to hardware standby mode is made according to the input level of the RES and
HSTBY pins.
In hardware standby mode, all chip functions are halted.
This state is exited by means of a power-on reset.
2. Software standby mode
A transition to software standby mode is made by means of software (a CPU instruction).
In software standby mode, all chip functions are halted.
This state is exited by means of a power-on reset or an NMI interrupt.
3. Sleep mode
A transition to sleep mode is made by means of a CPU instruction.
In software standby mode, basically only the CPU is halted, and all on-chip peripheral modules
operate.
This state is exited by means of a power-on reset, interrupt, or DMA address error.
Table 21.1 describes the transition conditions for entering the modes from the program execution
state as well as the CPU and peripheral function status in each mode and the procedures for
canceling each mode.
Rev. 5.00 Jan 06, 2006 page 641 of 818
REJ09B0273-0500