SH7050 Datasheet, PDF (725/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Bit
Bit Name
Value Description
3
Input capture/ 0
[Clearing condition]
(Initial value)
compare match
flag (IMF4A)
1
Read IMF4A when IMF4A =1, then write 0 in IMF4A
[Setting conditions]
1. TCNT4 value is transferred to GR4A by an input capture
signal when GR4A functions as an input capture register
2. TCNT4 = GR4A when GR4A functions as an output
compare register
2
Overflow flag 0
[Clearing condition]
(Initial value)
(OVF5)
Read OVF5 when OVF5 =1, then write 0 in OVF5
1
[Setting condition]
TCNT5 overflowed from H'FFFF to H'0000
1
Input capture/ 0
[Clearing condition]
(Initial value)
compare match
flag (IMF5B)
1
Read IMF5B when IMF5B =1, then write 0 in IMF5B
[Setting conditions]
1. TCNT5 value is transferred to GR5B by an input capture
signal when GR5B functions as an input capture register
2. TCNT5 = GR5B when GR5B functions as an output
compare register
0
Input capture/ 0
[Clearing condition]
(Initial value)
compare match
flag (IMF5A)
1
Read IMF5A when IMF5A =1, then write 0 in IMF5A
[Setting conditions]
1. TCNT5 value is transferred to GR5A by an input capture
signal when GR5A functions as an input capture register
2. TCNT5 = GR5A when GR5A functions as an output
compare register
Rev. 5.00 Jan 06, 2006 page 705 of 818
REJ09B0273-0500