SH7050 Datasheet, PDF (581/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 18 ROM (128 kB Version)
18.8 Protection
There are two kinds of flash memory program/erase protection, hardware protection and software
protection.
18.8.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in flash memory control register 1
(FLMCR1) and erase block register 1 (EBR1). The FLMCR1 and EBR1 settings are retained in
the error-protected state. (See table 18.7.)
Table 18.7 Hardware Protection
Item
FWE pin protection
Reset/standby
protection
Description
• When a low level is input to the FWE pin,
FLMCR1 and EBR1 are initialized, and the
program/erase-protected state is entered.
• In a reset (including a WDT overflow
reset) and in standby mode, FLMCR1 and
EBR1 are initialized, and the
program/erase-protected state is entered.
• In a reset via the RES pin, the reset state
is not entered unless the RES pin is held
low until oscillation stabilizes after
powering on. In the case of a reset during
operation, hold the RES pin low for the
RES pulse width specified in the AC
Characteristics section.
Functions
Program Erase
Yes
Yes
Yes
Yes
Rev. 5.00 Jan 06, 2006 page 561 of 818
REJ09B0273-0500