SH7050 Datasheet, PDF (314/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
H'FFFFFFFF
H'FFFFF800
H'00002800
H'00001800
H'00000800
H'00000000
CPU 0 write
to IIF1by user
program
Interrupt status
flag (IIF1)
Counter value
TCNT0
Time
Figure 10.18 Example of Interval Timer Operation
10.3.8 Twin-Capture Function
The ATU’s channel 0 ICR0A and channel 1 OSBR can be made to perform input capture in
response to the same trigger by means of a setting in timer I/O control register TIOR0A. When the
ATU channel 0 counter (TCNT0) and channel 1 counter (TCNT1) are started by a setting in the
timer status register (TSR), and a trigger signal is input from the ICR0A input capture input pin
(TIA0), the TCNT0 value can be transferred to ICR0A, and the TCNT1 value to OSBR. Rising-
edge, falling-edge, or both-edge detection can be selected for the TIA0 trigger input pin.
By making the appropriate setting in the timer interrupt enable register (TIER), an interrupt
request can be sent to the CPU when input capture occurs.
An example of twin-capture operation is shown in figure 10.19.
In the example in figure 10.19, twin-capture is started using a both-edge detection specification.
Rev. 5.00 Jan 06, 2006 page 294 of 818
REJ09B0273-0500