SH7050 Datasheet, PDF (281/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME5A): Enables or disables
interrupt requests by IMF5A in TSR when IMF5A is set to 1.
Bit 0:
IME5A
0
1
Description
IMI5A interrupt requested by IMF5A is disabled
IMI5A interrupt requested by IMF5A is enabled
(Initial value)
Timer Interrupt Enable Register E (TIERE)
TIERE controls enabling/disabling of channel 6 to 9 cycle register compare interrupt requests.
Bit: 7
6
5
4
3
2
1
0
— CME6 — CME7 — CME8 — CME9
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W
R
R/W
R
R/W
R
R/W
Bit 7—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 6—Cycle Register Compare-Match Interrupt Enable (CME6): Enables or disables
interrupt requests by CMF6 in TSR when CMF6 is set to 1.
Bit 6:
CME6
0
1
Description
CMI6 interrupt requested by CMF6 is disabled
CMI6 interrupt requested by CMF6 is enabled
(Initial value)
Bit 5—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 4—Cycle Register Compare-Match Interrupt Enable (CME7): Enables or disables
interrupt requests by CMF7 in TSR when CMF7 is set to 1.
Bit 4:
OME7
0
1
Description
CMI7 interrupt requested by CMF7 is disabled
CMI7 interrupt requested by CMF7 is enabled
(Initial value)
Bit 3—Reserved: This bit is always read as 0, and should only be written with 0.
Rev. 5.00 Jan 06, 2006 page 261 of 818
REJ09B0273-0500