SH7050 Datasheet, PDF (13/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

11.3.1 Overview.............................................................................................................. 349
11.3.2 Advanced Pulse Controller Output Operation ..................................................... 350
11.4 Usage Notes ...................................................................................................................... 353
Section 12 Watchdog Timer (WDT).............................................................................. 355
12.1 Overview........................................................................................................................... 355
12.1.1 Features................................................................................................................ 355
12.1.2 Block Diagram ..................................................................................................... 356
12.1.3 Pin Configuration................................................................................................. 356
12.1.4 Register Configuration......................................................................................... 357
12.2 Register Descriptions ........................................................................................................ 357
12.2.1 Timer Counter (TCNT)........................................................................................ 357
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 358
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 360
12.2.4 Register Access.................................................................................................... 361
12.3 Operation .......................................................................................................................... 362
12.3.1 Watchdog Timer Mode ........................................................................................ 362
12.3.2 Interval Timer Mode ............................................................................................ 364
12.3.3 Clearing the Standby Mode ................................................................................. 364
12.3.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 365
12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 365
12.4 Notes on Use ..................................................................................................................... 366
12.4.1 TCNT Write and Increment Contention .............................................................. 366
12.4.2 Changing CKS2 to CKS0 Bit Values................................................................... 366
12.4.3 Changing between Watchdog Timer/Interval Timer Modes................................ 366
12.4.4 System Reset With WDTOVF ............................................................................. 367
12.4.5 Internal Reset With the Watchdog Timer ............................................................ 367
Section 13 Serial Communication Interface (SCI) .................................................... 369
13.1 Overview........................................................................................................................... 369
13.1.1 Features................................................................................................................ 369
13.1.2 Block Diagram ..................................................................................................... 370
13.1.3 Pin Configuration................................................................................................. 371
13.1.4 Register Configuration......................................................................................... 371
13.2 Register Descriptions ........................................................................................................ 373
13.2.1 Receive Shift Register (RSR) .............................................................................. 373
13.2.2 Receive Data Register (RDR) .............................................................................. 373
13.2.3 Transmit Shift Register (TSR) ............................................................................. 374
13.2.4 Transmit Data Register (TDR)............................................................................ 374
13.2.5 Serial Mode Register (SMR)................................................................................ 375
13.2.6 Serial Control Register (SCR).............................................................................. 377
Rev. 5.00 Jan 06, 2006 page xiii of xx