SH7050 Datasheet, PDF (723/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Interrupt Enable Register DL H'FFFF8204
8
ATU
(TIERDL)
(Channels 3 to 5)
Bit:
Bit name:
Initial value:
R/W:
7
OVE4
0
R/W
6
IME4D
0
R/W
5
IME4C
0
R/W
4
IME4B
0
R/W
3
IME4A
0
R/W
2
OVE5
0
R/W
1
IME5B
0
R/W
0
IME5A
0
R/W
Bit
Bit Name
Value Description
7
Overflow interrupt enable 0
OVI4 interrupt requested by OVF4 flag is disabled
(OVE4)
(Initial value)
1
OVI4 interrupt requested by OVF4 flag is enabled
6
Input capture/compare 0
IMI4D interrupt requested by IMF4D flag is
match interrupt enable
disabled
(Initial value)
(IME4D)
1
IMI4D interrupt requested by IMF4D flag is enabled
5
Input capture/compare 0
IMI4C interrupt requested by IMF4C flag is
match interrupt enable
disabled
(Initial value)
(IME4C)
1
IMI4C interrupt requested by IMF4C flag is enabled
4
Input capture/compare 0
IMI4B interrupt requested by IMF4B flag is
match interrupt enable
disabled
(Initial value)
(IME4B)
1
IMI4B interrupt requested by IMF4B flag is enabled
3
Input capture/compare 0
IMI4A interrupt requested by IMF4A flag is
match interrupt enable
disabled
(Initial value)
(IME4A)
1
IMI4A interrupt requested by IMF4A flag is enabled
2
Overflow interrupt enable 0
OVI5 interrupt requested by OVF5 flag is disabled
(OVE5)
(Initial value)
1
OVI5 interrupt requested by OVF5 flag is enabled
1
Input capture/compare 0
IMI5B interrupt requested by IMF5B flag is
match interrupt enable
disabled
(Initial value)
(IME5B)
1
IMI5B interrupt requested by IMF5B flag is enabled
0
Input capture/compare 0
IMI5A interrupt requested by IMF5A flag is
match interrupt enable
disabled
(Initial value)
(IME5A)
1
IMI5A interrupt requested by IMF5A flag is enabled
Rev. 5.00 Jan 06, 2006 page 703 of 818
REJ09B0273-0500