SH7050 Datasheet, PDF (300/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
OSBR is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word
read.
OSBR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
For details, see sections 10.3.4, Input Capture Function.
10.2.17 Cycle Registers (CYLR)
The cycle registers (CYLR) are 16-bit registers. The ATU has four cycle registers, one each for
channels 6 to 9.
Channel
6
7
8
9
Abbreviation
CYLR6
CYLR7
CYLR8
CYLR9
Function
Cycle registers
Cycle Registers (CYLR6 to CYLR9)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage.
The CYLR value is constantly compared with the corresponding free-running counter (TCNT6 to
TCNT9) value, and when the two values match, the corresponding timer start register (TSR) bit
(CMF6 to CMF9) is set to 1, and the free-running counter (TCNT6 to TCNT9) is cleared. At the
same time, the buffer register (BFR) value is transferred to the duty register (DTR).
The CYLR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a word read or write.
The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode
and software standby mode.
For details of the CYLR, BFR, and DTR registers, see sections 10.3.9, PWM Timer Function.
Rev. 5.00 Jan 06, 2006 page 280 of 818
REJ09B0273-0500