SH7050 Datasheet, PDF (456/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
14.1.4 Register Configuration
Table 14.2 summarizes the A/D converter’s registers.
Table 14.2 A/D Converter Registers
Name
Abbreviation R/W
Initial
Value
Address
Access
Size^*1
A/D data register 0 (H/L)
ADDR0 (H/L) R
H'0000 H'FFFF85D0 8, 16
A/D data register 1 (H/L)
ADDR1 (H/L) R
H'0000 H'FFFF85D2 8, 16
A/D data register 2 (H/L)
ADDR2 (H/L) R
H'0000 H'FFFF85D4 8, 16
A/D data register 3 (H/L)
ADDR3 (H/L) R
H'0000 H'FFFF85D6 8, 16
A/D data register 4 (H/L)
ADDR4 (H/L) R
H'0000 H'FFFF85D8 8, 16
A/D data register 5 (H/L)
ADDR5 (H/L) R
H'0000 H'FFFF85DA 8, 16
A/D data register 6 (H/L)
ADDR6 (H/L) R
H'0000 H'FFFF85DC 8, 16
A/D data register 7 (H/L)
ADDR7 (H/L) R
H'0000 H'FFFF85DE 8, 16
A/D data register 8 (H/L)
ADDR8 (H/L) R
H'0000 H'FFFF85E0 8, 16
A/D data register 9 (H/L)
ADDR9 (H/L) R
H'0000 H'FFFF85E2 8, 16
A/D data register 10 (H/L)
ADDR10 (H/L) R
H'0000 H'FFFF85E4 8, 16
A/D data register 11 (H/L)
ADDR11 (H/L) R
H'0000 H'FFFF85E6 8, 16
A/D data register 12 (H/L)
ADDR12 (H/L) R
H'0000 H'FFFF85F0 8, 16
A/D data register 13 (H/L)
ADDR13 (H/L) R
H'0000 H'FFFF85F2 8, 16
A/D data register 14 (H/L)
ADDR14 (H/L) R
H'0000 H'FFFF85F4 8, 16
A/D data register 15 (H/L)
A/D control/status register 0
ADDR15 (H/L)
ADCSR0
R
H'0000
R/(W)^*2 H'00
H'FFFF85F6
H'FFFF85E8
8, 16
8, 16
A/D control register 0
A/D control/status register 1
ADCR0
ADCSR1
R/W H'1F
R/(W)^*2 H'00
H'FFFF85E9
H'FFFF85F8
8, 16
8, 16
A/D control register 1
ADCR1
R/W H'7F
H'FFFF85F9 8, 16
A/D trigger register
ADTRGR
R/W H'FF
H'FFFF83B8 8
Notes: Register accesses consist of 3 cycles for byte access and 6 cycles for word access.
1. A 16-bit access must be made on a word boundary.
2. Only 0 can be written in bit 7, to clear the flag.
Rev. 5.00 Jan 06, 2006 page 436 of 818
REJ09B0273-0500