SH7050 Datasheet, PDF (350/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Contention between GR Write and Data Transfer by Input Capture: If input capture occurs
in the T2 state of a CPU write cycle for a channel 1 to 5 general register (GR1A to GR1F, GR2A,
GR2B, GR3A to GR3D, GR4A to GR4D, GR5A, GR5B), the write to TCNT has priority and the
data transfer to GR is not performed.
Writing of 1 to the interrupt status flag due to input capture is performed in the same way as for
normal input capture.
The timing in this case is shown in figure 10.54.
CK
Address
T1
T2
GR address
Internal write signal
Internal input capture signal
GR
CPU write value
Interrupt status flag
Figure 10.54 Contention between GR Write and Data Transfer by Input Capture
Rev. 5.00 Jan 06, 2006 page 330 of 818
REJ09B0273-0500