SH7050 Datasheet, PDF (404/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode.
The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not
selected, or when the SCI is not transmitting.
Bit 0: MPBT
0
1
Description
Multiprocessor bit value in transmit data is 0 (initial value)
Multiprocessor bit value in transmit data is 1
13.2.8 Bit Rate Register (BRR)
The bit rate register (BRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write the BRR. The BRR is initialized to H'FF by a power-on reset,
in hardware standby mode and software standby mode. Each channel has independent baud rate
generator control, so different values can be set in the two channels.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 13.3 lists examples of BRR settings in the asynchronous mode; table 13.4 lists examples of
BBR settings in the clock synchronous mode.
Rev. 5.00 Jan 06, 2006 page 384 of 818
REJ09B0273-0500