SH7050 Datasheet, PDF (75/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 4 Clock Pulse Generator (CPG)
4.1.2 Pin Configuration
The pins relating to the clock pulse generator are shown in table 4.1.
Table 4.1 CPG Pins
Pin Name
External clock
Crystal
System clock
Mode setting
Mode setting
PLL power supply
PLL ground
PLL capacitance
Abbreviation
EXTAL
XTAL
CK
MD3
MD2
PLLV_CC
PLLV_SS
PLLCAP
I/O
Input
Input
Output
Input
Input
Input
Input
Input
Description
Crystal resonator or external clock input
Crystal resonator connection
System clock output
Sets PLL multiplication mode
Sets PLL multiplication mode
PLL multiplier circuit power supply
PLL multiplier circuit ground
PLL multiplier circuit oscillation external
capacitance pin
4.2 Clock Operating Modes
The clock operating mode is set with the MD3 and MD2 pins.
Clock mode selection is possible in operating modes 0 to 3 and 16 to 19. In this case, do not set
both the MD3 and MD2 pin to 1. In programmer mode, the clock operating mode cannot be
changed.
The relationship between the mode pins and the clock operating mode is shown in table 4.2.
Table 4.2 Clock Operating Mode Settings
Clock Mode MD3
MD2
Input
Frequency
Range (MHz)
Mode 0
0
0
4–10
Mode 1
0
1
4–10
Mode 2
1
0
4–5
Note: Crystal resonator and external clock input
PLL
Multiplication
Factor
×1
×2
×4
Operating
Frequency Range
(MHz)
4–10
8–20
16–20
For the chip operating frequency, a frequency of 1, 2, or 4 times the input frequency can be
selected as the internal clock by means of the on-chip PLL circuit. The system clock (CK pin)
output frequency is the same as that of the internal clock.
Rev. 5.00 Jan 06, 2006 page 55 of 818
REJ09B0273-0500