SH7050 Datasheet, PDF (815/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Bus Control Register 1 (BCR1)
Bit: 15
14
Bit name: —
—
Initial value: 0
0
R/W: R
R
Appendix A On-Chip Supporting Module Registers
H'FFFF8620
8/16/32
BSC
13
12
11
10
9
8
—
—
—
—
—
—
0
0
0
0
0
0
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
A3SZ A2SZ A1SZ A0SZ
Initial value: 0
0
0
0
1
1
1
1
R/W: R
R
R
R
R/W R/W R/W R/W
Bit
Bit Name
Value Description
3
CS3 space size
0
CS3 space has byte (8-bit) bus size
specification (A3SZ) ₁
CS3 space has word (16-bit) bus size (Initial value)
2
CS2 space size
0
CS2 space has byte (8-bit) bus size
specification (A2SZ) ₁
CS2 space has word (16-bit) bus size (Initial value)
1
CS1 space size
0
CS1 space has byte (8-bit) bus size
specification (A1SZ) ₁
CS1 space has word (16-bit) bus size (Initial value)
0
CS0 space size
0
CS0 space has byte (8-bit) bus size
specification (A0SZ) ₁
CS0 space has word (16-bit) bus size (Initial value)
Note: A0SZ is valid only in on-chip ROM enabled mode In on-chip ROM disabled mode, the bus
size for the CS0 space is set by the mode pins.
Rev. 5.00 Jan 06, 2006 page 795 of 818
REJ09B0273-0500