SH7050 Datasheet, PDF (463/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 14 A/D Converter
Bit 6—Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a
maximum of 266 states when CKS is 0, and a maximum of 134 states when 1. To prevent
incorrect operation, ensure that the ADST bit in A/D control register 0 (ADCR0) is cleared to 0
before changing the A/D conversion time. For details, see section 14.4.3, Analog Input Setting and
A/D Conversion Time.
Bit 6:
CKS
0
1
Description
Conversion time = 266 states (maximum)
Conversion time = 134 states (maximum)
(Initial value)
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when ADST
is set to 1, and stopped when ADST is cleared to 0.
Bit 5:
ADST
0
1
Description
A/D conversion is stopped
(Initial value)
A/D conversion is being executed
[Clearing conditions]
• Single mode: Automatically cleared to 0 when A/D conversion ends
• Scan mode: Cleared by writing 0 in ADST after confirming that ADF in ADCSR0
is 1
Note that the operation of the ADST bit differs between single mode and scan mode.
In single mode and scan mode, ADST is automatically cleared to 0 when A/D conversion ends on
one channel. However, in scan mode, when all conversions have ended for the selected analog
inputs, ADST remains set to 1 in order to start A/D conversion again for all the channels.
Therefore, the ADST bit must be cleared to 0, stopping A/D conversion, before changing the
conversion time or the analog input channel selection.
Ensure that the ADST bit in ADCR0 is cleared to 0 before switching the operating mode.
Also, make sure that A/D conversion is stopped (ADST is cleared to 0) before changing A/D
interrupt enabling (bit ADIE in ADCSR0), the A/D conversion time (bit CKS in ADCR0), the
operating mode (bits ADM1 and ADM0 in ADSCR), or the analog input channel selection (bits
CH3 to CH0 in ADCSR0). The A/D data register contents will not be guaranteed if these changes
are made while the A/D converter is operating (ADST is set to 1).
Bits 4 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Rev. 5.00 Jan 06, 2006 page 443 of 818
REJ09B0273-0500