SH7050 Datasheet, PDF (253/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bits 2 to 0—I/O Control 3A2 to 3A0, 3C2 to 3C0, 4A2 to 4A0, 4C2 to 4C0, 5A2 to 5A0
(IO3A2 to IO3A0, IO3C2 to IO3C0, IO4A2 to IO4A0, IO4C2 to IO4C0, IO5A2 to IO5A0):
These bits select the general register (GR) function.
Bit 2:
IOxx2
0
Bit 1:
IOxx1
0
Bit 0:
IOxx0
0
1
1
0
1
1
0
0
1
1
0
1
Description
GR is an output
compare register
GR is input capture
register
0 output regardless of compare-match
(Initial value)
0 output on GR compare-match
1 output on GR compare-match
Toggle output on GR compare-match
Input capture disabled
Input capture in GR on rising edge
Input capture in GR on falling edge
Input capture in GR on both rising and
falling edges
10.2.6 Trigger Selection Register (TGSR)
The trigger selection register (TGSR) is an 8-bit register. The ATU has one TGSR register.
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— TRG0D — TRG0A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W
R
R/W
TGSR is an 8-bit readable/writable register that selects an input pin (TIOA, TIOD) or the
compare-match output signal (TGR1A) from the channel 1 general register (GR1A) as the channel
0 input capture register (ICR0A, ICR0D) input trigger.
TGSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Rev. 5.00 Jan 06, 2006 page 233 of 818
REJ09B0273-0500