SH7050 Datasheet, PDF (282/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 2—Cycle Register Compare-Match Interrupt Enable (CME8): Enables or disables
interrupt requests by CMF8 in TSR when CMF8 is set to 1.
Bit 2:
CME8
0
1
Description
CMI8 interrupt requested by CMF8 is disabled
CMI8 interrupt requested by CMF8 is enabled
(Initial value)
Bit 1—Reserved: This bit is always read as 0, and should only be written with 0.
Bit 0—Cycle Register Compare-Match Interrupt Enable (CME9): Enables or disables
interrupt requests by CMF9 in TSR when CMF9 is set to 1.
Bit 0:
CME9
0
1
Description
CMI9 interrupt requested by CMF9 is disabled
CMI9 interrupt requested by CMF9 is enabled
(Initial value)
Timer Interrupt Enable Register F (TIERF)
TIERF controls enabling/disabling of channel 10 one-shot pulse interrupt requests.
Bit: 7
6
5
4
3
2
1
0
OSE10H OSE10G OSE10F OSE10E OSE10D OSE10C OSE10B OSE10A
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7—One-Shot Pulse Interrupt Enable (OSE10H): Enables or disables interrupt requests by
OSF10H in TSR when OSF10H is set to 1.
Bit 7:
OSE10H
0
1
Description
OSI10H interrupt requested by OSF10H is disabled
OSI10H interrupt requested by OSF10H is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 262 of 818
REJ09B0273-0500