SH7050 Datasheet, PDF (275/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 5—Input Capture/Compare-Match Interrupt Enable (IME1F): Enables or disables
interrupt requests by IMF1F in TSR when IMF1F is set to 1.
Bit 5:
IME1F
0
1
Description
IMI1F interrupt requested by IMF1F is disabled
IMI1F interrupt requested by IMF1F is enabled
(Initial value)
Bit 4—Input Capture/Compare-Match Interrupt Enable (IME1E): Enables or disables
interrupt requests by IMF1E in TSR when IMF1E is set to 1.
Bit 4:
IME1E
0
1
Description
IMI1E interrupt requested by IMF1E is disabled
IMI1E interrupt requested by IMF1E is enabled
(Initial value)
Bit 3—Input Capture/Compare-Match Interrupt Enable (IME1D): Enables or disables
interrupt requests by IMF1D in TSR when IMF1D is set to 1.
Bit 3:
IME1D
0
1
Description
IMI1D interrupt requested by IMF1D is disabled
IMI1D interrupt requested by IMF1D is enabled
(Initial value)
Bit 2—Input Capture/Compare-Match Interrupt Enable (IME1C): Enables or disables
interrupt requests by IMF1C in TSR when IMF1C is set to 1.
Bit 2:
IME1C
0
1
Description
IMI1C interrupt requested by IMF1C is disabled
IMI1C interrupt requested by IMF1C is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 255 of 818
REJ09B0273-0500