SH7050 Datasheet, PDF (286/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 3—Interval Interrupt Bit 3 (ITVE3): Interrupt controller (INTC) interval interrupt setting
bit corresponding to bit 13 in TCNT0L. The rise of bit 13 in TCNT0L is ANDed with ITVE3, the
result is stored in IIF3 in the timer status register (TSRAH), and an interrupt request is sent to
INTC.
Bit 3:
ITVE3
0
1
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
(Initial value)
Bit 2—Interval Interrupt Bit 2 (ITVE2): INTC interval interrupt setting bit corresponding to bit
12 in TCNT0L. The rise of bit 12 in TCNT0L is ANDed with ITVE2, the result is stored in IIF2 in
TSRAH, and an interrupt request is sent to INTC.
Bit 2:
ITVE2
0
1
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
(Initial value)
Bit 1—Interval Interrupt Bit 1 (ITVE1): INTC interval interrupt setting bit corresponding to bit
11 in TCNT0L. The rise of bit 11 in TCNT0L is ANDed with ITVE1, the result is stored in IIF1 in
TSRAH, and an interrupt request is sent to INTC.
Bit 1
ITVE1
0
1
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
(Initial value)
Bit 0—Interval Interrupt Bit 0 (ITVE0): INTC interval interrupt setting bit corresponding to bit
10 in TCNT0L. The rise of bit 10 in TCNT0L is ANDed with ITVE0, the result is stored in IIF0 in
TSRAH, and an interrupt request is sent to INTC.
Bit 0:
ITVE0
0
1
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
(Initial value)
For details, see section 10.3.7, Interval Timer Operation.
Rev. 5.00 Jan 06, 2006 page 266 of 818
REJ09B0273-0500