SH7050 Datasheet, PDF (245/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bits 2 to 0—Clock Select 2B to 0B (CKSEL2B to CKSEL0B): These bits select clock φ", scaled
from the internal clock source, for DCNT10G and DCNT10H in channel 10, from φ', φ'/2, φ'/4,
φ'/8, φ'/16, and φ'/32. DCNT10G and DCNT10H count on the same synchronous clock.
Bit 2:
Bit 1:
Bit 0:
CKSEL2B CKSEL1B CKSEL0B Description
0
0
0
Internal clock φ": counting on φ'
1
Internal clock φ": counting on φ'/2
1
0
Internal clock φ": counting on φ'/4
1
Internal clock φ": counting on φ'/8
1
0
0
Internal clock φ": counting on φ'/16
1
Internal clock φ": counting on φ'/32
1
0
Cannot be set
1
Cannot be set
(Initial value)
10.2.5 Timer I/O Control Registers (TIOR)
The timer I/O control registers (TIOR) are 8-bit registers. The ATU has ten TIOR registers, one
for channel 0, three for channel 1, one for channel 2, two each for channels 3 and 4, and one for
channel 5.
Channel
0
1
2
3
4
5
Abbreviation
TIOR0A
TIOR1A,
TIOR1B,
TIOR1C
TIOR2A
TIOR3A,
TIOR3B
TIOR4A,
TIOR4B
TIOR5A
Function
ICR0 and OSBR edge detection setting
GR1 and GR2 input capture/compare-match switching, edge
detection/output value setting
GR3 to GR5 input capture/compare-match switching, edge
detection/output value setting, TCNT3 to TCNT5 clear
enable/disable setting
Each TIOR is an 8-bit readable/writable register used to select the functions of dedicated input
capture registers and general registers.
For dedicated input capture registers (ICR), TIOR performs edge detection setting.
Rev. 5.00 Jan 06, 2006 page 225 of 818
REJ09B0273-0500