SH7050 Datasheet, PDF (811/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
User Break Bus Cycle Register (UBBR)
H'FFFF8608
8/16/32
UBC
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
Bit name: CP1 CP0
ID1
ID0 RW1 RW0 SZ1 SZ0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
Value Description
7, 6
CPU cycle/peripheral 0 0 User break interrupt not generated (Initial value)
cycle select
(CP1, CP0)
1 CPU cycle taken as the break condition
1 0 Peripheral cycle taken as the break condition
1 CPU cycle and peripheral cycle both taken as break
conditions
5, 4
Instruction fetch/data 0 0 User break interrupt not generated (Initial value)
access select
(ID1, ID0)
1 Instruction fetch cycle taken as the break condition
1 0 Data access cycle taken as the break condition
1 Instruction fetch cycle and data access cycle both
taken as break conditions
3, 2
Read/write select
(RW1, RW0)
0 0 User break interrupt not generated (Initial value)
1 Read cycle taken as the break condition
1 0 Write cycle taken as the break condition
1 Read and write cycles both taken as break conditions
1, 0
Operand size select 0 0 Operand size not included in the break condition
(SZ1, SZ0)
(Initial value)
1 Byte access taken as the break condition
1 0 Word access taken as the break condition
1 Longword access taken as the break condition
Rev. 5.00 Jan 06, 2006 page 791 of 818
REJ09B0273-0500