SH7050 Datasheet, PDF (263/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 0—Input Capture/Compare-Match Flag (IMF2A): Status flag that indicates GR2A input
capture or compare-match.
Bit 0:
IMF2A
0
1
Description
[Clearing condition]
(Initial value)
When IMF2A is read while set to 1, then 0 is written in IMF2A
[Setting conditions]
• When the TCNT2 value is transferred to GR2A by an input capture signal while
GR2A is functioning as an input capture register
• When TCNT2 = GR2A while GR2A is functioning as an output compare register
Timer Status Registers DH and DL (TSRDH, TSRDL)
TSRDH indicates the status of channel 3 input capture, compare-match, and overflow.
Bit: 7
6
5
4
—
—
—
OVF3
Initial value: 0
0
0
0
R/W: R
R
R R/(W)*
Note: * Only 0 can be written, to clear the flag.
3
IMF3D
0
R/(W)*
2
IMF3C
0
R/(W)*
1
IMF3B
0
R/(W)*
0
IMF3A
0
R/(W)*
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Flag (OVF3): Status flag that indicates TCNT3 overflow.
Bit 4:
OVF3
0
1
Description
[Clearing condition]
When OVF3 is read while set to 1, then 0 is written in OVF3
[Setting condition]
When the TCNT3 value overflows (from H'FFFF to H'0000)
(Initial value)
Rev. 5.00 Jan 06, 2006 page 243 of 818
REJ09B0273-0500