SH7050 Datasheet, PDF (166/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Bits 11–8—Resource Select 3–0 (RS3–RS0): These bits specify the transfer request source.
Bit 11: Bit 10: Bit 9: Bit 8:
RS3
RS2 RS1 RS0 Description
0
0
0
0
External request, dual address mode (initial value)
0
0
0
1
Prohibited
0
0
1
0
External request, single address mode. External address
space → external device.
0
0
1
1
External request, single address mode. External device →
external address space.
0
1
0
0
Auto-request
0
1
0
1
Prohibited
0
1
1
0
ATU, compare-match 6 (CMI6)
0
1
1
1
ATU, input capture 0B (ICI0B)
1
0
0
0
SCI0 transmission
1
0
0
1
SCI0 reception
1
0
1
0
SCI1 transmission
1
0
1
1
SCI1 reception
1
1
0
0
SCI2 transmission
1
1
0
1
SCI2 reception
1
1
1
0
On-chip A/D0
1
1
1
1
On-chip A/D1
Note: External request designations are valid only for channels 0 and 1. No transfer request
sources can be set for channels 2 or 3.
Bit 6—DREQ Select (DS): Sets the sampling method for the DREQ pin in external request mode
to either low-level detection or falling-edge detection. This bit is valid only with CHCR0 and
CHCR1. For CHCR2 and CHCR3, this bit always reads as 0 and cannot be modified.
Even with channels 0 and 1, when specifying an on-chip peripheral module or autorequest as the
transfer request source, this bit setting is ignored. The sampling method is fixed at falling-edge
detection in cases other than auto-request.
Bit 6: DS
0
1
Description
Low-level detection (initial value)
Falling-edge detection
Rev. 5.00 Jan 06, 2006 page 146 of 818
REJ09B0273-0500