SH7050 Datasheet, PDF (42/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 2 CPU
2.1.2 Control Registers
The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR),
and vector base register (VBR). The status register indicates processing states. The global base
register functions as a base address for the indirect GBR addressing mode to transfer data to the
registers of on-chip peripheral modules. The vector base register functions as the base address of
the exception processing vector area (including interrupts). Figure 2.2 shows a control register.
31
SR
31
31
9 8 7 6 5 4 321 0
M Q I3 I2 I1 I0 S T
SR: Status register
T bit: The MOVT, CMP/cond, TAS, TST,
BT (BT/S), BF (BF/S), SETT, and CLRT
instructions use the T bit to indicate true
(1) or false (0). The ADDV, ADDC,
SUBV, SUBC, DIV0U, DIV0S, DIV1,
NEGC, SHAR, SHAL, SHLR, SHLL,
ROTR, ROTL, ROTCR, and ROTCL
instructions also use the T bit to indicate
carry/borrow or overflow/underflow.
S bit: Used by the MAC instruction.
Reserved bits. This bit always read 0.
The write value should always be 0.
Bits I0–I3: Interrupt mask bits.
M and Q bits: Used by the DIV0U, DIV0S,
and DIV1 instructions.
Reserved bits. 0 is read. Write only.
GBR
0 Global base register (GBR):
Indicates the base address of the indirect
GBR addressing mode. The indirect GBR
addressing mode is used in data transfer
for on-chip peripheral modules register
areas and in logic operations.
VBR
0 Vector base register (VBR):
Stores the base address of the exception
processing vector area.
Figure 2.2 Control Register Configuration
Rev. 5.00 Jan 06, 2006 page 22 of 818
REJ09B0273-0500