SH7050 Datasheet, PDF (304/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Channels 3, 4, and 5: ATU channels 3 and 4 each have a 16-bit free-running counter (TCNT3,
TCNT4) and four 16-bit general registers (GR3A to GR3D, GR4A to GR4D). TCNT3 and
TCNT4 are up-counters that perform free-running operation. The four general registers (GR3A to
GR3D, GR4A to GR4D) each have corresponding external signal I/O pins (TIOA3 to TIOD3,
TIOA4 to TIOD4, TIOA5, TIOB5), and can be used as input capture or output compare-match
registers.
With channels 3 and 4, GR3D and GR4D are automatically designated as cycle registers by setting
PWM mode in the timer mode register (TMDR). In PWM mode, the counter is automatically
cleared by an output compare-match when the GR3D/GR4D value matches the TCNT3/TCNT4
value. Therefore, channels 3 and 4 can each be used as 3-channel PWM timers, with GR3A to
GR3C or GR4A to GR4C as the duty registers, and GR3D or GR4D as the cycle register.
Channel 5 has a 16-bit counter (TCNT5) and two 16-bit general registers (GR5A and GR5B).
Channel 5 can perform the same kind of operations as channel 3, the only difference being in the
number of general registers. In PWM mode, GR5A is designated as the duty register and GR5B as
the cycle register.
Channels 6, 7, 8, and 9 (Dedicated PWM Timers): ATU channels 6 to 9 each have a 16-bit free-
running counter (TCNT6 to TCNT9), 16-bit cycle register (CYLR6 to CYLR9), 16-bit duty
register DTR6 to DTR9), and buffer register (BFR6 to BFR9). Each of channels 6 to 9 also has an
external output pin (TO6 to TO9), and can be used as a buffered PWM timer. TCNT6 to TCNT9
are up-counters, and 0 is output to the corresponding external output pin when the TCNT value
matches the DTR value (when DTR ≠ H'0000). When the TCNT value matches the CYLR value
(when DTR ≠ H'0000), 1 is output to the external output pin, TCNT is initialized to H'0001, and
the BFR value is transferred to DTR. Thus, the configuration of channels 6 to 9 enables them to
perform waveform output with the CYLR value as the cycle and the DTR value as the duty, and to
use BFR to absorb the time lag between setting of data in DTR and compare-match occurrence.
The relationship between the pins and registers is shown in table 10.4.
When DTR ≥ CYLR, 1 is output continuously to the external output pin, giving a duty of 100%.
When DTR = H'0000, 0 is output continuously to the external output pin, giving a duty of 0%.
Channel 10: ATU channel 10 has eight 16-bit down-counters (DCNT10A to DCNT10H), and
corresponding external output pins (TOA10 to TOH10). One-shot pulse output can be performed
by setting the DCNT value, starting DCNT operation in the user program and outputting 1 to the
external output pin, then halting the count operation when DCNT underflows, and outputting 0 to
the external output pin.
By coupling the operation with the channel 1 or channel 2 output compare function, offset one-
shot pulse output can be performed, whereby a one-shot pulse is generated by starting DCNT
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