SH7050 Datasheet, PDF (126/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 7 User Break Controller (UBC)
7.4.2 Break on CPU Data Access Cycle
1. Register settings:
Conditions set:
UBARH = H'0012
UBARL = H'3456
UBBR = H'006A
Address: H'00123456
Bus cycle: CPU, data access, write, word
A user break interrupt occurs when word data is written into address H'00123456.
2. Register settings:
Conditions set:
UBARH = H'00A8
UBARL = H'0391
UBBR = H'0066
Address: H'00A80391
Bus cycle: CPU, data access, read, word
A user break interrupt does not occur because the word access was performed on an even address.
7.4.3 Break on DMA/DTC Cycle
1. Register settings:
Conditions set:
UBARH = H'0076
UBARL = H'BCDC
UBBR = H'00A7
Address: H'0076BCDC
Bus cycle: DMA, data access, read, longword
A user break interrupt occurs when longword data is read from address H'0076BCDC.
2. Register settings:
Conditions set:
UBARH = H'0023
UBARL = H'45C8
UBBR = H'0094
Address: H'002345C8
Bus cycle: DMA, instruction fetch, read
(operand size not included in conditions)
A user break interrupt does not occur because no instruction fetch is performed in the DMA/CTC
cycle.
Rev. 5.00 Jan 06, 2006 page 106 of 818
REJ09B0273-0500