SH7050 Datasheet, PDF (422/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 13 Serial Communication Interface (SCI)
1
Serial
data
TDRE
Start
bit
0 D0
Data
Parity Stop Start
bit bit bit
D1 D7 0/1 1 0 D0
Data
Parity Stop
bit bit
1
D1 D7 0/1 1 ^Idle
(marking
state)
TEND
TxI
interrupt
request
TxI interrupt
handler writes
data in TDR
and clears
TDRE to 0
1 frame
TxI
request
TEI interrupt request
Example: 8-bit data with parity and one stop bit
Figure 13.6 SCI Transmit Operation in Asynchronous Mode
Receiving Serial Data (Asynchronous Mode): Figures 13.7 and 13.8 show a sample flowchart
for receiving serial data. The procedure is as follows (the steps correspond to the numbers in the
flowchart).
1. SCI initialization: Set the RxD pin using the PFC.
2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,
and FER bits of the SSR to identify the error. After executing the necessary error handling,
clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain
set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.
3. SCI status check and receive-data read: Read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. Continue receiving serial data: Read the RDR and RDRF bit and clear RDRF to 0 before the
stop bit of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RxI) to read RDR, the RDRF bit is cleared automatically so this step is unnecessary.
Rev. 5.00 Jan 06, 2006 page 402 of 818
REJ09B0273-0500