SH7050 Datasheet, PDF (105/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 6 Interrupt Controller (INTC)
Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.4 Interrupt Request Sources and IPRA–IPRH
Register
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Interrupt priority register G
Interrupt priority register H
15–12
IRQ0
IRQ4
DMAC0, 1
ATU03
ATU2
ATU42
ATU102
SCI0
11–8
IRQ1
IRQ5
DMAC2, 3
ATU11
ATU31
ATU5
ATU103
SCI1
Bits
7–4
IRQ2
IRQ6
ATU01
ATU12
ATU32
ATU6–9
CMT0, A/D0
SCI2
3–0
IRQ3
IRQ7
ATU02
ATU13
ATU41
ATU101
CMT1, A/D1
WDT
As indicated in table 6.4, four IRQ pins or groups of 4 on-chip peripheral modules are allocated to
each register. Each of the corresponding interrupt priority ranks are established by setting a value
from H'0 (0000) to H'F (1111) in each of the four-bit groups 15–12, 11–8, 7–4 and 3–0. Interrupt
priority rank becomes level 0 (lowest) by setting H'0, and level 15 (highest) by setting H'F. If
multiple on-chip peripheral modules are assigned to same bit (DMAC0 and DMAC1, DMAC2
and DMAC3, ATU6 to ATU9, CMT0 and A/D0, and CMT1 and A/D1), those multiple modules
are set to the same priority rank.
IPRA–IPRH are initialized to H'0000 by a power-on reset. They are not initialized in standby
mode.
Rev. 5.00 Jan 06, 2006 page 85 of 818
REJ09B0273-0500