SH7050 Datasheet, PDF (168/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel.
Bit 0: DE
0
1
Description
Operation of the corresponding channel disabled (initial value)
Operation of the corresponding channel enabled
Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3–RS0 settings).
With an external request or on-chip module request, when a transfer request occurs after this bit is
set to 1, transfer is enabled. If this bit is cleared during a data transfer, transfer is suspended.
If the DE bit has been set, but TE = 1, then if the DME bit of the DMAOR is 0, and the NMI or
AE bit of the DMAOR is 1, transfer enable mode is not entered.
9.2.5 DMAC Operation Register (DMAOR)
The DMAOR is a 16-bit read/write register that specifies the transfer mode of the DMAC. Bits
15–10 and bits 7–3 of this register always read as 0 and cannot be modified.
Register values are initialized to 0 by a power-on reset and in software standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
PR1 PR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
Bit: 7
6
5
4
3
2
—
—
—
—
—
AE
Initial value: 0
0
0
0
0
0
R/W: R
R
R
R
R
R/(W)^*
Note: * 0 write only is valid after 1 is read at the AE and NMIF bits.
1
NMIF
0
R/(W)^*
0
DME
0
R
Rev. 5.00 Jan 06, 2006 page 148 of 818
REJ09B0273-0500