SH7050 Datasheet, PDF (746/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Appendix A On-Chip Supporting Module Registers
Timer Status Register B (TSRB)
H'FFFF82C5 (Channel 1) 8
ATU
Bit: 7
6
5
4
Bit name: —
OVF1 IMF1F IMF1E
Initial value: 0
0
0
0
R/W: R R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written to clear the flag.
3
IMF1D
0
R/(W)*
2
IMF1C
0
R/(W)*
1
IMF1B
0
R/(W)*
0
IMF1A
0
R/(W)*
Bit
Bit Name
Value Description
6
Overflow flag
(OVF1)
0
[Clearing condition]
(Initial value)
Read OVF1 when OVF1 =1, then write 0 in OVF1
1
[Setting condition]
TCNT1 overflowed from H'FFFF to H'0000
5
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF1F)
1
Read IMF1F when IMF1F =1, then write 0 in IMF1F
[Setting conditions]
1. TCNT1 value is transferred to GR1F by an input
capture signal when GR1F functions as an input
capture register
2. TCNT1 = GR1F when GR1F functions as an output
compare register
4
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF1E)
1
Read IMF1E when IMF1E =1, then write 0 in IMF1E
[Setting conditions]
1. TCNT1 value is transferred to GR1E by an input
capture signal when GR1E functions as an input
capture register
2. TCNT1 = GR1E when GR1E functions as an output
compare register
3
Input capture/
0
[Clearing condition]
(Initial value)
compare match flag
(IMF1D)
1
Read IMF1D when IMF1D =1, then write 0 in IMF1D
[Setting conditions]
1. TCNT1 value is transferred to GR1D by an input
capture signal when GR1D functions as an input
capture register
2. TCNT1 = GR1D when GR1D functions as an output
compare register
Rev. 5.00 Jan 06, 2006 page 726 of 818
REJ09B0273-0500