SH7050 Datasheet, PDF (278/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 10 Advanced Timer Unit (ATU)
Bit 3—Input Capture/Compare-Match Interrupt Enable (IME3D): Enables or disables
interrupt requests by IMF3D in TSR when IMF3D is set to 1.
Bit 3:
IME3D
0
1
Description
IMI3D interrupt requested by IMF3D is disabled
IMI3D interrupt requested by IMF3D is enabled
(Initial value)
Bit 2—Input Capture/Compare-Match Interrupt Enable (IME3C): Enables or disables
interrupt requests by IMF3C in TSR when IMF3C is set to 1.
Bit 2:
IME3C
0
1
Description
IMI3C interrupt requested by IMF3C is disabled
IMI3C interrupt requested by IMF3C is enabled
(Initial value)
Bit 1—Input Capture/Compare-Match Interrupt Enable (IME3B): Enables or disables
interrupt requests by IMF3B in TSR when IMF3B is set to 1.
Bit 1:
IME3B
0
1
Description
IMI3B interrupt requested by IMF3B is disabled
IMI3B interrupt requested by IMF3B is enabled
(Initial value)
Bit 0—Input Capture/Compare-Match Interrupt Enable (IME3A): Enables or disables
interrupt requests by IMF3A in TSR when IMF3A is set to 1.
Bit 0:
IME3A
0
1
Description
IMI3A interrupt requested by IMF3A is disabled
IMI3A interrupt requested by IMF3A is enabled
(Initial value)
Rev. 5.00 Jan 06, 2006 page 258 of 818
REJ09B0273-0500