SH7050 Datasheet, PDF (185/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 9 Direct Memory Access Controller (DMAC)
External memory space → External memory space
(External memory space has 16-bit width)
CK
A21–A0
Transfer
source
address (H)
Transfer
source
address (L)
NOP
Indirect
address
Transfer
destination
address
CSn
D15–D0
Internal
address
bus
Internal
data bus
DMAC
indirect
address
buffer
DMAC
data
buffer
RD
WRH,
WRL
Indirect
address (H)
Indirect
address (L)
Transfer source
address ^∗1
NOP
Transfer source address ^∗2
Transfer
data
Transfer
data
Indirect
address
Transfer Transfer
data
data
Indirect
address
Transfer
data
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
Data
write cycle
(3rd)
(4th)
Notes: 1. The internal address bus is controlled by the port and does not change.
2. DMAC does not fetch value until 32-bit data is read from the internal data
bus.
Figure 9.10 Dual Address Mode and Indirect Address Transfer Timing Example 1
Rev. 5.00 Jan 06, 2006 page 165 of 818
REJ09B0273-0500