SH7050 Datasheet, PDF (150/841 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/

Section 8 Bus State Controller (BSC)
8.4.2 Simplification of Bus Cycle Start Detection
For consecutive accesses of the same CS space, waits are inserted so that the number of idle cycles
designated by the CW3 to CW0 bits of the BCR2 occur. However, for write cycles after reads, the
number of idle cycles inserted will be the larger of the two values defined by the IW and CW bits.
When idle cycles already exist between access cycles, waits are not inserted. Figure 8.8 shows an
example. A continuous access idle is specified for CSn space, and CSn space is consecutively
write accessed.
T₁
T₂
T_idle
T₁
T₂
CK
Address
CSn
RD
WRx
Data
CSn space access
Idle cycle
CSn space access
Figure 8.8 Same Space Consecutive Access Idle Cycle Insertion Example
Rev. 5.00 Jan 06, 2006 page 130 of 818
REJ09B0273-0500