SH-2A Datasheet, PDF (91/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

unsigned long
unsigned long
unsigned long
};
SR structure definition
dummy2:2;
S0:1;
T0:1;
#define BO ((* (struct SR0 *) (&SR)).BO0)
#define CS ((* (struct SR0 *) (&SR)).CS0)
#define M ((* (struct SR0 *) (&SR)).M0)
#define Q ((* (struct SR0 *) (&SR)).Q0)
#define I ((* (struct SR0 *) (&SR)).I0)
#define S ((* (struct SR0 *) (&SR)).S0)
#define T ((* (struct SR0 *) (&SR)).T0)
Definition of bits in SR
Error (char *er);
Error indication function
Section 6 Instruction Descriptions
These are floating-point number definition statements.
#define PZERO
0
#define NZERO
1
#define DENORM
2
#define NORM
3
#define PINF
4
#define NINF
5
#define qNaN
6
#define sNaN
7
#define EQ
0
#define GT
1
#define LT
2
#define UO
3
#define INVALID
4
#define FADD
0
#define FSUB
1
#define CAUSE
0x0003f000 /* FPSCR(bit17-12) */
Rev. 3.00 Jul 08, 2005 page 77 of 484
REJ09B0051-0300