SH-2A Datasheet, PDF (199/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

6.4.16
DIV0S
Initialization for
Signed Division
DIVide (step 0) as Signed
Section 6 Instruction Descriptions
Arithmetic Instruction
Format
DIV0S Rm,Rn
Abstract
MSB of Rn → Q, MSB of Rm → M,
M^Q → T
Code
Cycle T Bit
0010nnnnmmmm0111 1
Calculation result
Description
DIV0S is an initialization instruction for signed division. It finds the quotient by repeatedly
dividing in combination with the DIV1 or another instruction that divides for each bit after this
instruction. See the description given with DIV1 for more information.
Operation
DIV0S(long m,long n)
/* DIV0S Rm,Rn */
{
if ((R[n]&0x80000000)==0) Q=0;
else Q=1;
if ((R[m]&0x80000000)==0) M=0;
else M=1;
T=!(M==Q);
PC+=2;
}
Example: See DIV1.
Rev. 3.00 Jul 08, 2005 page 185 of 484
REJ09B0051-0300