SH-2A Datasheet, PDF (480/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 8 Pipeline Operation
Operation
• Single-Precision
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after five stages
– IF, DF, E1, E2, SF. Contention may occur if an instruction that reads the destination of one
of these instructions is located within the 5 instructions following that instruction.
• Double-Precision
The CPU pipeline ends after three stages – IF, ID, EX – and the FPU pipeline after 10 stages –
IF, DF, E1, E1, E1, E1, E1, E1, E2, SF. Contention may occur if an instruction that reads the
destination of one of these instructions is located within the 15 instructions following that
instruction.
Instruction Issuance
These instructions use the FPU arithmetic operation pipeline. See section 8.6, Contention Due to
FPU, for details of contention.
Parallel Execution Capability
No particular comments
Rev. 3.00 Jul 08, 2005 page 466 of 484
REJ09B0051-0300