SH-2A Datasheet, PDF (116/501 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Section 6 Instruction Descriptions
6.3.8
BSET
Bit Set
Bit SET
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Format
Abstract
Code
BSET.B #imm3, @(disp12,Rn) 1 → (<imm> of (disp+Rn)) 0011nnnn0iii10010001dddddddddddd
BSET #imm3, Rn
1 → <imm> of Rn
10000110nnnn1iii
Cycle
3
1
T Bit
—
—
Description
Sets to 1 a specified bit of memory at the address indicated by (disp + Rn), or of the LSB 8 bits of
a general register Rn. The bit number is specified by 3-bit immediate data. With the BSET.B
instruction, after data is read from memory as a byte unit, the specified bit is set to 1, and the
resulting data is then written to memory as a byte unit.
BSET.B #imm3, @(disp12, Rn)
Specified by #imm3
7
0
(disp+Rn)
1
BSET #imm3, Rn
31
Rn
Lower 8 bits specified
by #imm3
7
0
1
Rev. 3.00 Jul 08, 2005 page 102 of 484
REJ09B0051-0300